The present invention relates to a demodulator to demodulate a data signal from an FSK (Frequency Shift Keying) signal in a transmission system for and, more particularly, to an FSK signal demodulator suitable in the form of a digital integrated circuit.
Such a kind of technique is disclosed in, for example, "Analog and Communications Products Data Book", pp. 9.22 to 9.42, Advanced Micro Devices, Inc., 1983.
In addition, an apparatus in the form of a digital integrated circuit FSK signal demodulating apparatus is disclosed in JP-A-54-87465. FIG. 2 herein shows main sections of this prior art apparatus and FIG. 3 shows a waveform in each section. A data signal such as shown at waveform 3a in FIG. 3 is modulated with FSK modulation, and the resulting signal is converted into pulse train such as a waveform 2a in FIG. 3 by a band pass filter 1 and a slicer 2. This pulse train is converted into a pulse train of a constant pulse width such as waveform 2b by a pulse width adjusting circuit 21. This pulse train is as a reset pulse to a counter 22. A pulse train waveform 2c, having a sufficiently higher-speed than the waveform 2b, is input from an oscillator 23 to a clock input of the counter 22. In FIG. 3, waveform 3b denotes the operation of the counter 22. This diagram shows a change in count number as an axis of ordinate. It is determined by a decision circuit 24 whether the counter output is "1" or "0" using as a reference value the count level indicated by the alternate long and short dash line in waveform 3b of FIG. 3. The resultant data becomes a waveform as shown in waveform 2d. This signal is filtered by a low pass filter 25 to eliminate the influence of noise, so that a signal of waveform 2e is derived. This signal is waveform shaped by a waveform reshaper 26 to thereby form a pulse. A data signal clock output 2g is extracted by a timing detection circuit 28. A data signal output such as a waveform 2f is obtained by a regenerator 27.
The demodulating accuracy of the foregoing demodulator is detected by the ratio of the carrier frequency of the FSK signal and the frequency of the counter clock (waveform 2c in FIG. 3) from the oscillator 23. As the counter clock frequency is higher than the FSK carrier frequency, the allowance for the discriminating count number is large as shown in FIG. 3b in FIG. 3. The allowance for noise is large, and the demodulation can be performed with a high demodulating accuracy. However, when considering the semiconductor device and circuit technique which are used, the counter clock frequency cannot be set to a high value without limitation. When the counter clock frequency is set to about 10 MHz, the carrier frequency is at most about 100 kHz and the transmission data signal speed is about a few kb/sec. It is impractical to transmit a data signal of a speed higher than that value by the transmission system using the foregoing demodulator.
Further, the conventional apparatus needs averaging with the low pass filter 25 and has a drawback such that the whole demodulator cannot be formed of only logic circuits.